1. Field of the Invention
The invention relates to input structures for switched-capacitor circuits. More particularly, the invention relates to switched-capacitor input circuits for limiting input noise. Yet more particularly, the invention relates to input structures for switched-capacitor circuits which limit input noise while not appreciably distorting the sampled input signal and without degrading the settling time of circuits downstream of the input structure.
2. Related Art
Representative conventional switched-capacitor input structures are illustrated schematically in FIGS. 1 and 2. In both of these conventional switched-capacitor input structures, an input voltage V.sub.IN is sampled onto. An input capacitor C.sub.IN through switch S.sub.IN during a first input phase. During a second input phase, switch S.sub.IN changes state to disconnect the input voltage V.sub.IN from capacitor C.sub.IN. Either the charge or the voltage accumulated on capacitor C.sub.IN is then transferred from the input capacitor C.sub.IN to a next stage of circuitry (not shown). In each of the circuits of FIGS. 1 and 2, the switch S.sub.SAMPLE also switches state when the input structure switches between the first phase, referred to hereinafter as the sampling phase, and the second phase, referred to hereinafter as the hold phase. During the sample phase, switch S.sub.SAMPLE is in a conductive state, while during hold phase, switch S.sub.SAMPLE is in a substantially non-conductive state. Another switch S.sub.H connects the input side of C.sub.IN to a bias voltage V.sub.H during hold phase and is substantially non-conducting during sample phase. Switches S.sub.IN, S.sub.H and S.sub.SAMPLE are controlled by a sampling clock (not shown). The clock signal may be connected to gate terminals of MOS transistors forming the switches.
In the circuit of FIG. 1 the voltage V.sub.IN is sampled with respect to a bias voltage V.sub.B. In the circuit of FIG. 2 V.sub.IN is sampled with respect to the offset voltage of op amp AMP, which will facilitate offset compensation of op amp AMP. When S.sub.SAMPLE is in a substantially conducting state, i.e., sample phase, op amp AMP is connected in a unity gain configuration. Thus, any input offset voltage is subtracted from the voltage transferred to capacitor C.sub.IN. In this configuration, the input offset error voltage of op amp AMP is compensated because the inverting input of op amp AMP remains connected to input capacitor C.sub.IN when switch S.sub.SAMPLE is in a substantially non-conducting state, i.e., during hold phase. The input offset voltage previously subtracted from the voltage transferred is thus added back in during hold phase, fully compensating for the input offset voltage.
One important characteristic of these input structures is bandwidth. Components downstream of the input structures are usually required to have extremely wide bandwidths, in order to slew and settle quickly. For example, in the sample phase, sample and hold circuits or sigma-delta modulators are required to accurately track variations in the input signal. In addition, in hold phase, these circuits are required to settle rapidly. The input structure illustrated in FIG. 1 has a dominant pole at ##EQU1## The resistance R.sub.SWITCH is the ON resistance of switch S.sub.IN, while the resistance R.sub.SAMPLE is the ON resistance of switch S.sub.SAMPLE. Capacitance C.sub.S is the value of capacitor C.sub.IN. The dominant pole of the circuit of FIG. 2 occurs at ##EQU2## In the definition of .tau..sub.B, R.sub.SWITCH and C.sub.S are defined as above, while G.sub.M is the transconductance of op amp AMP. As an example, for a switched capacitor input on a 12-bit analog-to-digital (A/D) converter sampling at a 10MHz rate, typical values achievable for the various components and typical target dominant pole frequencies are given in the table below.
TABLE 1 ______________________________________ Value ______________________________________ R.sub.SWITCH 10-50 .OMEGA. R.sub.SAMPLE 100-500 .OMEGA. C.sub.S 1-10 pF G.sub.M 1-10 mA/V .omega..sub.A 20-400 MHz .omega..sub.B 20-400 MHz ______________________________________
In these prior art circuits, if the input voltage is noisy, then that noise is sampled by the input capacitor. Given a wide bandwidth system, the input noise is not significantly limited. Systems for certain applications require wide bandwidth for good distortion performance in the sample phase. In addition, systems typically are designed to have a bandwidth wide enough so that the system settles quickly enough during hold phase to suit a particular application. As a result, input noise may be sampled into the system, if not in some way limited or prevented from being present at the input. Sources of input noise can include thermal noise of a source circuit that drives the input voltage V.sub.IN or noise from unrelated circuits coupling into the input voltage V.sub.IN.
In prior art circuits such as FIGS. 1 and 2, there is a tradeoff between noise and distortion depending on the value of R.sub.SWITCH. When the resistance R.sub.SWITCH of switch S.sub.IN is large, the bandwidth of the system is small and the system may not settle quickly enough. When R.sub.SWITCH is small, the bandwidth of the system is large, and noise coupling may be introduced from the input voltage. The nominal value of R.sub.SWITCH is a design parameter set by the designer, but the actual value of R.sub.SWITCH during circuit operation varies substantially with the input voltage, V.sub.IN, producing distortion due to the input transfer function being non-linear. Typical prior art systems operating on an input signal having a spectral bandwidth of between 20 and 40 megahertz may have a bandwidth of approximately 400 megahertz to accommodate settling time requirements. However, the noise bandwidth of a system designed to the parameters described above is unacceptably large.
FIG. 3 schematically illustrates an example of a differential prior-art switched-capacitor input structure which samples an input voltage onto input capacitors C.sub.INP and C.sub.INM during the sample phase. The input voltage is impressed across the input terminals V.sub.INP and V.sub.INM. The embodiment of FIG. 3 includes a differential sample switch S.sub.SAMPLE which connect capacitors C.sub.INP and C.sub.INM together during the sample phase and also includes two additional switches, S.sub.SAMPLEP and S.sub.SAMPLEM, which connect capacitors C.sub.INP and C.sub.INM to bias voltage V.sub.B during the sample phase. Two switches, S.sub.HP and S.sub.HM, are turned on during the hold phase to charge the input terminals of capacitors C.sub.INP and C.sub.HM to V.sub.HP and V.sub.HM. In some implementations of this prior-art circuit, V.sub.HP and V.sub.HM may be at substantially the same potential. FIG. 4 illustrates another prior-art switched-capacitor input structure which is similar to the embodiment of FIG. 3. The embodiment of FIG. 4 differs from that of FIG. 3 in that a single switch, S.sub.H, is used in place of the two switches, S.sub.HP and S.sub.HM, of the embodiment of FIG. 3. This single switch, S.sub.H, forces the input terminals of capacitors C.sub.INP and C.sub.INM to the same potential during hold phase by connecting them together.
FIG. 5 illustrates another prior-art differential switched-capacitor input structure. The circuit of FIG. 5 includes sample switches S.sub.SAMPLEP and S.sub.SAMPLEM which connect the amplifier AMP in unity-gain configuration during the sample phase in order to charge the input capacitors with respect to the offset voltage of the amplifier AMP. This allows offset compensation of the amplifier. Two switches, S.sub.HP and S.sub.HM, are turned on during the hold phase to charge the input terminals of capacitors C.sub.INP and C.sub.INM to V.sub.HP and V.sub.HM. In some implementations of this prior-art circuit, V.sub.HP and V.sub.HM may be at substantially the same potential. FIG. 6 illustrates another differential embodiment of a prior-art switched-capacitor input structure which is similar to the embodiment of FIG. 5. The embodiment of FIG. 6 differs from that of FIG. 5 in that a single switch, S.sub.H, is used in place of the two switches, S.sub.HP and S.sub.HM, of the embodiment of FIG. 5. This single switch, S.sub.H, forces the input terminals of capacitors C.sub.INP and C.sub.INM to the same potential during hold phase by connecting them together.
FIGS. 7 and 8 schematically show prior art solutions to the noise coupling problems associated with FIG. 1. In FIG. 7, resistor R.sub.EXT is added between the input voltage source and switch S.sub.IN Resistor R.sub.EXT is much larger than the resistance of switch S.sub.IN and therefore dominates the input resistance. Thus, the external resistance dominates the pole .omega..sub.A. However, non-linearities continue to plague the prior art systems.
The solution of FIG. 8 adds an external resistor R.sub.EXT and external capacitor C.sub.EXT. By setting the values of the external capacitor and external resistor appropriately, the location of the pole .omega..sub.B can be set to suit a particular application. Here also, non-linearity plagues the system.
The drawbacks associated with the solutions of FIGS. 7 and 8 relate to the fact that when the external resistance is added upstream of the input switch S.sub.IN the non-linear parasitic capacitances of the input switch become problematic. In other words, the non-linear parasitic capacitances of the input switch cause distortion. Typically the input switch S.sub.IN is implemented as an MOS transmission gate switch. FIG. 9 schematically represents the input structure, showing some of the parasitic capacitances of a MOS-implemented transmission gate switch S.sub.IN that cause non-linear behavior and distortion with the addition of the external resistance.